Ct and mri image reconstruction based single-path delay feedback (sdf) fft pipeline architecture

Ravindrakumar Selvaraj, Suresh Kumar Pittala, Shaik Sadulla, Eswara Chaitanya Duvvuri

Abstract


Purpose: In radiology, several medical imaging modalities were used. In recent Biomedical systems, integrated circuits were used in the form of Application Specific Integrated Circuits (ASICs) to perform FFT. The raw data obtained from the acquiring equipment are reconstructed to image using Fast Fourier Transform (FFT). The contribution in the paper is to design an FFT integrated unit for converting the Magnetic Resonance (MR) signal into frequency spectrum of each phase encoding.
Materials and Methods: The image created is been transformed from the spatial projection using inverse Fourier transform. The k-space FFT information were back projected to obtain the MRI image. This paper presents an integrated circuit implementation of FFT processing elements used in Magnetic Resonance Imaging (MRI) reconstruction and ultrasonic imaging. The circuits designed in this work is to be used in the back-projection unit of MRI reconstruction. The complex periodic signal received from the receiver coils in MRI or piezoelectric disc in ultrasound and detector array in CT are analyzed using Fourier transform. The proposed single-path delay feedback (SDF) Decimation In Frequency (DIF) 4096-point FFT for image reconstruction was implemented in 65nm FPGA kit and programmed using VHDL in Quartus tool.
Results: This block becomes the part of the reconstruction unit of MRI image. The proposed design reduces the execution of instruction per cycle and the fixed point arithmetic provides low roundoff error.
Conclusions: Since in MRI reconstruction the frequency encoding and phase encoding is combined to develop the images the proposed FFT will be useful. In Future application specific integrated circuits will be designed for the entire MRI back projection and reconstruction unit.


Keywords


FFT, CT, MRI, Image Reconstruction, Pipeline Architecture, FinFET, Adder

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DOI: http://dx.doi.org/10.36162/hjr.v9i2.561

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